In fabrication of semiconductor devices, traditional methods attempting to reduce a color density difference between two complementary exposure masks include using coloring assignments or using colored dummy fill and fill stitches. However, coloring assignments are often times overly restrictive; due to design rule constraints, changing coloring assignments would require a complete redesign of the IC design. In addition, changing color assignments can perturb a design hierarchy of an IC design. For example, each instantiation of a standard cell in a large chip may require a different coloring due to a change in context, and, therefore, the hierarchy cannot be preserved. This lack of design hierarchy slows down the runtime of standard IC design tools, such as design-rule-check engines and automated routers, which increases the overall design cycle time. Relying on a dummy fill to insert colored polygons into white spaces of an IC design allows more design flexibility than coloring assignments. However, as the density of IC designs increases with scaling of each technology node, availability of white spaces decreases. Fill stitches, which are colored polygons inserted in wide metal lines, have also been proposed to mitigate density balance. However, due to the scaling of designs with each technology node, wide metal lines may not be used.
A need therefore exists for a methodology enabling a reduction of a density difference between two complementary exposure masks of a DPT process allowing design flexibility in IC designs, particularly high density IC designs, and an apparatus for performing the method.